The present invention relates to a full-adder circuit fabricated into a semiconductor integrated circuit, and more particularly to a full-adder circuit structured with CMOS FETs (complementary metal oxide field effect transistors).
A one-bit full-adder circuit of the CMOS FET type as prior art will be discussed referring to FIG. 1. In the figure, the full-adder circuit is comprised of a summing section for producing a summed output S, which includes a first exclusive OR circuit 1 and a second exclusive OR circuit 2, and a carry section 3 for producing a carry output Co as the result of an overflow. In the summing section, the first exclusive OR circuit 1 has two inputs, an addend input A, and an augend input B. The second exclusive OR circuit 2 also has two inputs, the output of the first exclusive OR circuit 1, and a carry input Ci. Structurally, the first exclusive OR circuit 1 is made up of a plurality of N channel MOS FETs, a plurality of P channel MOS FETs, and two MOS inverters I1 and I2. Similarly, the second exclusive OR circuit 2 is made up of a plurality of N channel MOS FETs, a plurality of P channel MOS FETs, and two MOS inverters I3 and I4. The carry section 3 is made up of a plurality of N channel MOS FETs, a plurality of P channel MOS FETs, and an inverter I5.
In the prior art full-adder circuit, the summing section uses as many as five stages of gates in the route, ranging from an input port for the augend B to an output port for the summed output S. During the adding operation, these gate stages respectively perform charging and discharging operations. Therefore, the use of many gates deteriorates the operation speed. The summing section and the carry section are entirely different from each other in the circuit arrangement. This fact suggests that two entirely different circuit patterns should be designed for these circuits in using integrated circuit technology, which requires a large pattern area. Further, five stages of gates are used in the summing section, but only two stages of the gates are used for the carry section. With the difference in number of the gate stages between those circuit sections, the summed output S and the carry output Co are produced at different timings. This timing difference creates other problems. For example, in designing a parallel multiplier, it is difficult to speed up the operation speed when it uses such a full-adder circuit. The different timing problems of the prior art full-adder circuit limit the applications of the full-adder circuit.